Verification Engineer Jobs in Chicago, IL

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Senior Verification Engineer

Avance Consulting

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Lisle, Illinois, USA

Full-time

Role: Senior Verification Engineer Location: Lisle IL (Day 1 On-site) In this role, the person will work in the Base software Verification & Validation team as a Sr. Engineer and play a significant role in verification and troubleshooting of unit/functional automated testing solutions, accountable for the overall unit/functional test automation strategy and test execution; and play a critical role as verification lead engineer in platform BSW (Basic Software) team as well. Responsibilities: Dev
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Posted 3 days ago | Updated 1 day ago

Senior Verification Engineer

VDart, Inc.

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Lisle, Illinois, USA

Contract, Third Party

Role: Senior Verification Engineer Location: Lisle IL Onsite Project In this role, the person will work in the Base software Verification & Validation team as a Sr. Engineer and play a significant role in verification and troubleshooting of unit/functional automated testing solutions, accountable for the overall unit/functional test automation strategy and test execution; and play a critical role as verification lead engineer in platform BSW (Basic Software) team as well. Responsibilities: Dev
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Posted 2 days ago | Updated 13 hours ago

Senior ASIC / FPGA Design Verification Engineer

Technical Link

•

Remote

Contract

6 Months Fully remote Verification RESPONSIBILITIES The senior verifier will be called upon to: develop SystemVerilog (or VHDL) test benches for the verification of ASICs or FPGAs;apply the various techniques and approaches of the Universal Verification Methodology (UVM);contribute to the development of the test infrastructure;document and report problems found to designers and assist them in identifying the source of the problems;support laboratory testing.QUALIFICATIONS Experience in writing
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Posted 60+ days ago | Updated 1 day ago

ASIC Verification Engineer

Q1 Technologies, Inc.

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Remote or Santa Clarita, California, USA

Full-time, Third Party, Contract

Job Title : ASIC Verification Engineer Location: Bay Area, CA & Austin, Texas (Onsite only) Opening 10 Mandatory Skills: Design Verification, UVM, IP, SOC, System Verilog Job Description: Experience in pre-silicon RTL Verification /IP Verification / SOC verification Strong knowledge of System Verilog and working knowledge of recent verification methodologies (UVM) Domain expertise in one or more of the following areas System-on-a-chip verification with multiple CPUs and fixed function units