A leaked Intel roadmap gives additional detail on the proposed ship dates of Intel’s next microprocessors, including the next Xeon Phi coprocessors and the “Avoton” system-on-a-chip for microservers that Intel detailed last year.
Intel’s roadmap, published by error on Intel’s own site, was picked up by CPU World, which published the Google cache of the documents; sites such as Wccftech.com also wrote about it. While the roadmap appears to be legitimate, Intel adjusts its schedules periodically, so it’s difficult to know whether or not whether the final shipping schedule will match up with the leaked copy.
What the roadmap shows, however, aligns with Intel’s plans as described last September by Diane Bryant, vice president and general manager of the Datacenter and Connected Systems Group at Intel. In 2013, Intel was scheduled to replace the low-voltage Xeon E3 server chip with the new architecture of the “Haswell” family—a chip that Intel designed for the ground up for the low-power constraints of ultrabooks (and presumably micro-servers). Around the same timeframe, Intel will launch its second-generation Atom SOC, the 22-nm “Avoton,” which will include an integrated network fabric.
According to the leaked server/roadmap summary slide, Haswell or the Xeon E3-1200, is due this quarter. Intel lists about thirteen different SKUs to support it, ranging from the E3-1285 to the E3-1220, plus low-power alternatives (“L”) for several. Haswell’s launch date is given as sometime between May 27 and June 7.
During the third quarter, Intel will launch the Xeon E5-2600 or “Ivy Bridge-EP” family, followed by the Xeon E7 or Ivy Bridge EX family in the fourth quarter. The slide lists the ‘Avoton” chip as shipping in the second half of 2013.
In the first quarter of 2014, the roadmap adds two new Xeon families: the E5-4600 (Ivy Bridge-EP 45) and the E5-2400 (Ivy Bridge-EN). Both are listed as preliminary and incomplete.
Intel also lists five new Xeon Phi coprocessors which should begin shipping in May: the 5120D, 3120A, 3120P, 7120P, and 7120X; without supplementary specification information, we can tell little except that Intel has identified them as a “speedbump,” meaning that they’re probably enhanced versions of existing products. The Xeon Phi has been used as a supplementary coprocessor in HPC applications, boosting overall computational power.
Intel also plans to launch its fourth-generation Core (Haswell) desktop microprocessors in the same May 27 to June 7 window, including a combined total of fourteen Core i7 and Core i5 processors. Intel also plans to release some additional third-generation Core i3 chips on June 9, together with new Pentium and Celeron offerings. That’s about the same timeframe that Intel plans to launch the mobile version of the Haswell chips as well, the slides say. A new Atom chip for tablets, Bay Trail-T, is due about September.
Years ago, a leaked Intel roadmap might make the pages of The Wall Street Journal; now, it barely matters for most PC users. Datacenter operators, however, should know that a speed bump is on the horizon—that is, if they don’t have it already, as part of a test deployment.