Chip designer ARM has whipped the curtain back from its CoreLink CCN-504, a low-power cache-coherent network can deliver a terabit of bandwidth per second via a high-speed interface. That could help improve the performance of ARM chips relative to the x86 infrastructure that currently dominates the data center. ARM licensees for the technology include Calxeda and LSI Logic. The CoreLink CCN-504 enables system coherency in heterogeneous multicore and multi-cluster CPU/GPU systems by enabling each processor in the system to access the other processor caches, ARM said. Specifically, the CCN-504 includes an integrated level 3 cache of up to 16MB, extending the ARM processor’s existing on-chip cache for demanding workloads and offering low latency on-chip memory for allocation and sharing of data between processors. The cache snooping function can access the data stored by those other cores in their own caches. The upshot of all this is a reduced need to access off-chip DRAM memory, increasing performance and reducing the power demand on DRAM, the most power-hungry component within the data center. The CCN-504 supports both the current-generation high-end Cortex-A15 processor and future eighth-generation ARMv8 processors ,and is the first in a family of network-based interconnect products planned by ARM. In case DRAM access is needed, however, ARM also announced the CoreLink DMC-520 dynamic memory controller, designed and optimized to work with the CoreLink CCN-504. The new dynamic memory controller provides a high-bandwidth interface to shared off-chip memory, such as DDR3, DDR3L and DDR4 DRAM. ARM said that it will be part of an integrated ARM DDR4 interface solution incorporating ARM Artisan DDR4/3 PHY IP planned for introduction in 2013. As most data center operators know, ARM sits at the intersection of a growing demand to lower the power used by data centers, but not at the expense of performance. ARM’s challenge, therefore, has been to maintain its traditional power advantage while increasing its computational performance, all in the name of competing better against Intel. Of course, there’s the question of how much market share ARM will capture: Gartner, for example, has offered some doubts about it seizing a substantial part of the market. With its new technology, ARM has suggested it’s building for the future. “As the amount of data used increases exponentially over the next 10-15 years, the CoreLink CCN-504 and DMC-520 will play an important role by providing high-performance system IP solutions for many-core applications,” Tom Cronk, deputy general manager, processor division of ARM, wrote in a statement. “This ensures quality of service and coherent operation across the system, and enables SoC designers to efficiently prioritize and handle wide data flows with optimum latency.” Image: ARM ARM CoreLink Aims to Accelerate Data Center
Chip designer ARM has whipped the curtain back from its CoreLink CCN-504, a low-power cache-coherent network can deliver a terabit of bandwidth per second via a high-speed interface. That could help improve the performance of ARM chips relative to the x86 infrastructure that currently dominates the data center. ARM licensees for the technology include Calxeda and LSI Logic. The CoreLink CCN-504 enables system coherency in heterogeneous multicore and multi-cluster CPU/GPU systems by enabling each processor in the system to access the other processor caches, ARM said. Specifically, the CCN-504 includes an integrated level 3 cache of up to 16MB, extending the ARM processor’s existing on-chip cache for demanding workloads and offering low latency on-chip memory for allocation and sharing of data between processors. The cache snooping function can access the data stored by those other cores in their own caches. The upshot of all this is a reduced need to access off-chip DRAM memory, increasing performance and reducing the power demand on DRAM, the most power-hungry component within the data center. The CCN-504 supports both the current-generation high-end Cortex-A15 processor and future eighth-generation ARMv8 processors ,and is the first in a family of network-based interconnect products planned by ARM. In case DRAM access is needed, however, ARM also announced the CoreLink DMC-520 dynamic memory controller, designed and optimized to work with the CoreLink CCN-504. The new dynamic memory controller provides a high-bandwidth interface to shared off-chip memory, such as DDR3, DDR3L and DDR4 DRAM. ARM said that it will be part of an integrated ARM DDR4 interface solution incorporating ARM Artisan DDR4/3 PHY IP planned for introduction in 2013. As most data center operators know, ARM sits at the intersection of a growing demand to lower the power used by data centers, but not at the expense of performance. ARM’s challenge, therefore, has been to maintain its traditional power advantage while increasing its computational performance, all in the name of competing better against Intel. Of course, there’s the question of how much market share ARM will capture: Gartner, for example, has offered some doubts about it seizing a substantial part of the market. With its new technology, ARM has suggested it’s building for the future. “As the amount of data used increases exponentially over the next 10-15 years, the CoreLink CCN-504 and DMC-520 will play an important role by providing high-performance system IP solutions for many-core applications,” Tom Cronk, deputy general manager, processor division of ARM, wrote in a statement. “This ensures quality of service and coherent operation across the system, and enables SoC designers to efficiently prioritize and handle wide data flows with optimum latency.” Image: ARM 
